In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits with a greater number of layers and with higher device densities. To achieve these high densities there have been, and continue to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish higher device packing densities, thinner layers, more uniform layers, smaller feature sizes, and smaller separations between features are required. This can include the thickness of gate oxide materials, (e.g., silicon oxide, metal oxides and high K materials such as ZrO2 and HfO2, etc.), interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. Thus, controlling the width, thickness and/or uniformity of layers created during the layering process can be important to the reliable operation of such integrated circuits.
Insulation and conductivity between electrically active regions is particularly important in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor devices. MOSFET devices typically include a gate separated from a substrate by a gate oxide. The thickness of the gate oxide can be important to reliable operation of the MOSFET, and thus, manufacturing the gate oxide to precise measurements facilitates increased MOSFET reliability. The gate oxide layer functions as an insulating layer, and can be the smallest feature of a device. Reducing the thickness of the gate oxide layer can contribute to increasing the switching speed of a transistor. However, reducing the thickness of the gate oxide layer can lead to problems associated with breakdown and reliability of gate oxides. Thus, precisely monitoring and controlling properties of the gate oxide layer including, but not limited to, thickness and uniformity, are important to facilitating reliable operation of the MOSFET. For example, the ability to store data, to retain data, to be erased, to be reprogrammed and to operate in desired electrical and temperature ranges can be affected by the thickness and/or uniformity of the gate oxide layer. However, due to non-uniform and uncontrolled gate oxide layer formation and inaccurate gate oxide layer formation monitoring techniques, a thickness of gate oxide may be formed greater or lesser than the thickness desired.
U.S. Pat. No. 6,727,995 issued to Halliyal et al. on Apr. 27, 2004, entitled “Gate Oxide Thickness Measurement and Control using Scatterometry,” which is hereby incorporated by reference, discloses a technique for regulating gate oxide thickness using reflected light to measure thickness and uniformity. However, such systems have detection limitations that limit the ability to measure ultra thin layers. Accordingly, a need exists for a solution that can characterize parameters, such as thicknesses, of ultra thin layers (i.e., films).